Overview
Every synchronous system needs a clock, and as interfaces and converters get faster, the quality of that clock matters more. Renesas supplies one of the broadest timing portfolios in the industry, from programmable clock generators to buffers and jitter attenuators, and BeiLuo supplies them as an authorized Renesas distributor with FAE support for clock design.
One Device for Several Clocks
A modern board often needs several clocks for its interfaces, its converters and its processor, and a programmable clock generator such as the 5P49V6975 produces multiple configurable output frequencies from a single reference. That replaces several fixed oscillators with one device, which reduces the board area and the bill of materials and simplifies the design. The configuration can be stored on-chip, so the device starts up correctly without external programming, which removes a source of production error.
Configuration and Flexibility
Because the outputs are configurable, one device can serve several products or several versions of a product, which simplifies inventory and reduces the number of parts to qualify. The flexibility also lets a design change its clock frequencies without a board change, which is valuable when an interface or a converter is updated.
Jitter and Phase Noise
Jitter and phase noise affect high-speed interfaces and data converters, because the timing error appears directly in the link or the measurement. A clock with low jitter preserves the performance of the interface or the converter it drives, and a clock with high jitter can limit a system that is otherwise capable. Choosing the clock for the jitter the system tolerates is therefore part of the signal-chain design, not an afterthought.
Measuring Jitter
Jitter should be measured with the real load and the real layout, because the load and the routing affect the result. A figure measured into a test load can differ from what the interface sees, so the measurement must reflect the real conditions. BeiLuo's FAE team can measure the clock in our lab.
Reference and Layout
The reference and the layout decide the jitter you achieve as much as the device does. Keep the reference close and clean, use a solid ground, and route the clock outputs as controlled-impedance traces away from the noise sources such as the switching supplies. A clock routed near a switching regulator will carry that noise into the interface it drives, so the layout deserves the same care as the electrical design.
Why BeiLuo
We hold mainstream Renesas timing parts in regional stock and ship them with import, origin and RoHS documentation. Our engineers support clock configuration, reference and layout design from concept through production, and we can measure the jitter in our lab.
Validating the Clock
Before production, measure the jitter with the real load and the real layout, confirm the output frequencies, and check the clock's immunity to the board's noise. The reference and the routing affect the result as much as the device, so the measurement must reflect the real conditions, and it is cheaper to take before the board is committed.
Next Steps
Send your output, frequency and jitter requirements and we will propose a clock set, confirm availability, and supply samples for validation.